Semiconductor devices such as processors, non-volatile memory, and other circuits include semiconductor elements such as metal oxide semiconductor field effect transistors (MOSFETS), diodes, resistors, and capacitors. For example, flash memory devices employ millions of floating gate FETs and processors employing millions of complementary MOSFETS. MOSFETS are generally disposed in active regions disposed in a base layer or substrate. Active regions typically include heavily doped silicon or other semiconductor regions. The regions can be doped with impurities such as phosphorous (P), boron (B), arsenic (As), or other impurities.
Semiconductor elements such as floating gate transistors and FETs are generally bulk semiconductor-type devices in contrast to semiconductor-on-insulator-type devices such as silicon-on-insulator (SOI) devices. The floating gate transistors and FETs are disposed in a single plane (e.g., a single active layer) on a top surface of a semiconductor substrate such as a single crystal silicon substrate.
Semiconductor-on-insulator (SOI) (e.g., silicon-on-insulator) devices have significant advantages over bulk semiconductor-type devices, including near ideal subthreshold voltage slope, elimination of latch-up, low junction capacitance, and effective isolation between devices. SOI-type devices generally completely surround a silicon or other semiconductor substrate with an insulator. Devices such as conventional FETs or other transistors are disposed on the silicon substrate by doping source and drain regions and by providing gate conductors between the source and drain regions. SOI devices provide significant advantages, including reduced chip size or increased chip density because minimal device separation is needed due to the surrounding insulating layers. Additionally, SOI devices can operate at increased speeds due to reduction in parasitic capacitance. These advantages are particularly important as integration technologies reach sub-100 nanometer levels for CMOS devices.
Conventional SOI devices generally have a floating substrate (i.e., the substrate is often totally isolated by insulating layers). SOI devices can be subject to floating substrate effects, including current and voltage kinks, thermal degradation, and large threshold voltage variations. Generally, SOI devices can include a very thin (200-800 Å thick) silicon film separated from a bulk substrate by a thick buried oxide (e.g., a 2000-3000 Å thick BOX layer).
Strained silicon (SMOS) processes are utilized to increase transistor (e.g., MOSFET) performance by increasing the carrier mobility of silicon, thereby reducing resistance and power consumption and increasing drive current, frequency response and operating speed. Strained silicon is typically formed by growing a layer of silicon on a silicon germanium substrate or layer. Germanium can also be implanted, deposited, or otherwise provided to silicon layers to change the lattice structure of the silicon and increase carrier mobility.
The silicon germanium lattice associated with the germanium substrate is generally more widely spaced than a pure silicon lattice, with spacing becoming wider with a higher percentage of germanium. Because the silicon lattice aligns with the larger silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. Relaxed silicon has a conductive band that contains six equal valance bands. The application of tensile strength to the silicon causes four of the valance bands to increase in energy and two of the valance bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus, lower energy bands offer less resistance to electron flow.
In addition, electrons meet with less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1,000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon compared to relaxed silicon, providing an increase in mobility of 80 percent or more for electrons and 20 percent or more for holes. The increase in mobility has been found to persist for current fields up to 1.5 megavolt/centimeter. These factors are believed to enable device speed increase of 35 percent without further reduction of device size, or a 25 percent reduction in power consumption without reduction in performance.
Heretofore, it has been difficult to manufacture SMOS devices on SOI substrates. Generally, providing a suitable strained silicon layer above an insulative substrate to achieve the advantage of an SOI substrate can be problematic. In addition, providing a strained silicon layer thin enough for a fully depleted MOSFET above an insulative layer can be difficult using conventional processes. A fully depleted MOSFET is a transistor for which the depletion region encompasses the entire or nearly the entire channel region.
Thus, there is a need for an SOI and strained semiconductor device. Further, there is a need for an SOI device which includes a strained silicon layer. Further still, there is a need for method of manufacturing an SOI structure including a strained silicon layer. Yet further, there is a need for a fully depleted transistor which has some of the advantages of SOI devices and SMOS devices. Even further, there is a need for an efficient method of manufacturing an SMOS device on an insulative substrate. Further still, there is a need for an efficient process for fabricating fully depleted SMOS SOI transistors.